[plug] ia64 linux = P4? & general Q re speed and if anyone has tried it

[Greg Mildenhall]

On Thu, 4 Oct 2001, Mike wrote:
> At 06:27 PM 4/10/2001 +0800, you wrote:
> >>Isn't that meant to be Intel's CISC architecture ???
> >No. Although intel did make CISC CPUs, that completely stopped at the 
> >Pentium range of CPUs which use RISC.
> <hrrrm> The conventional issue about RISC is the reduced number of
> instructions for simple decoding by the cpu's instruction decoder.
> Just because the cpu can decode instructions in one clock cycle
> does not necessarily make the CPU a 'RISC' design when it inherently
> has to cope with CISC type instructions - which have a huge "set" !

"Reduced instruction set" doesn't necessarily have to refer to the
instruction set it reads in from RAM. If the core of the processor is
running RISC microcode, then the CISC instructions it is translating don't
stop the core from being RISC. What is the instruction set of a Pentium
running a JVM?

Also remember that RISC denotes a set of reduced instructions, not a
reduced set of instructions. The number of instructions is not relevant.

-Greg